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  1 april 1998 HMP8115 ntsc/pal video decoder features ? (m) ntsc and (b, d, g, h, i, m, n, n c ) pal operation - optional auto detect of video standard - itu-r bt.601 (ccir601) and square pixel operation ? digital output formats - vmi compatible - 8-bit, 16-bit 4:2:2 ycbcr - 15-bit (5,5,5), 16-bit (5,6,5) rgb - linear or gamma-corrected - 8-bit bt.656 ? analog input formats - three analog composite inputs - analog y/c (s-video) input ? sliced vbi data capture capabilities - closed captioning - widescreen signalling (wss) - bt.653 system b, c and d teletext - nabts (north american broadcast teletext) - wst (world system teletext) ? 2-line (1h) comb filter y/c separator ? fast i 2 c interface ? two 8-bit adcs applications ? multimedia pcs ? video conferencing ? video compression systems ? video security systems ? lcd projectors and overhead panels ? related products - ntsc/pal encoders: hmp815x, hmp817x - ntsc/pal decoders: hmp8112a ? related literature - an9644: composite video separation techniques - an9716: widescreen signalling - an9717: ycbcr to rgb considerations - an9728: bt.656 video interface for ics - an9738: vmi video interface for ics description the HMP8115 is a high quality ntsc and pal decoder with internal a/d converters. it is compatible with ntsc m, pal b, d, g, h, i, m, n, and combination n (n c ) video standards. both composite and s-video (y/c) input formats are sup- ported. a 2-line comb ?lter plus a user-selectable chromi- nance trap ?lter provide high quality y/c separation. user adjustments include brightness, contrast, saturation, hue, and sharpness. data during the vertical blanking interval (vbi), such as closed captioning, widescreen signalling and teletext, may be captured and output as bt.656 ancillary data. closed captioning and widescreen signalling information may also be read out via the i 2 c interface. ordering information part number temp. range ( o c) package pkg. no. HMP8115cn 0 to 70 80 ld pqfp q80.14x20 hmpvideval/isa evaluation board: isa frame grabber notes: 1. pqfp is also known as qfp and mqfp. 2. evaluation board and reference design descriptions are in the applications section. caution: these devices are sensitive to electrostatic discharge. users should follow proper ic handling procedures. http://www.intersil.com or 407-727-9207 | copyright ? intersil corporation 1999 file number 4283.5
2 table of contents pag e introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 external video processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 analog video inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 anti-aliasing filters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 s-video chroma gain control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 digitization of video . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 a/d conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 agc and dc restoration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 input signal detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 vertical sync and field detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 y/c separation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 input sample rate converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 comb filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 chroma demodulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 output sample rate converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 clk2 input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 digital processing of video . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 uv to cbcr conversion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 digital color gain control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 color killer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 y processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 cbcr processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 ycbcr output format processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 rgb output format processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 built-in video generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 pixel port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 hsync and vsync timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 field timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 blank and d v alid timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 pixel output port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 8-bit ycbcr output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 16-bit ycbcr, 15-bit rgb, or 16-rgb output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 8-bit bt.656 output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 advanced features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 closed captioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 widescreen signalling (wss) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 bt.656 ancillary data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 bt.656 closed captioning and wide screen signalling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 teletext . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 real time control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 host interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 HMP8115 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 pcb layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 evaluation board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 related application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 electrical speci?cations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 HMP8115 HMP8115
3 functional block diagram p[15:0] blank field d v alid user adjust color trap output sample rate converter locked input mux white peak level digital comparators black level sync level 8-bit adc agc clamp and ntsc-pal1 ntsc-pal2 ntsc-pal3/y l_cap lagc_cap yout yin + - clamp digital comparator 8-bit adc clamp c c_cap gain_ctrl + - sda scl reset gain control logic and line pll vsync detect microprocessor interface and control hsync vsync logic color demodulation y/c separation input sample rate converter chroma pll hsync detect lock color adjust external antialiasing filter external antialiasing filter vbi detection and decoding logic vbiv alid intreq user adjust. output timing and fifo rgb logic vbi status bits HMP8115
4 HMP8115 functional block diagram (continued) y,cvbs c cr[7:0] m u x chroma line comb c,cvbs data y data enable y data chroma demodulator y data c,cvbs data c data y data u,v saturation adjust sharpness adjust standard select m u x hsync detect chroma phase detector chroma pll nco 4fsc clock clk (24.54, 27.0 or 29.5mhz) line locked pll loop filter hue adjust agc adjust vsync detect input rate converter sample filter delay trap clk to 4fsc ratio hsync vsync genlock loss locked field sync and contrast adjust brightness, stripper, output rate converter sample line locked nco chroma pll loop filter horizontal and vertical sharpness adjust u, v to cbcr color converter and color killer space m u x enable lp filter enable lp filter cbcr y rgb logic output fifo and timing mux mux p[15:0] hsync, vsync, blank, field, d v alid, vbiv alid vbi detection and decoding logic
5 introduction the HMP8115 is designed to decode baseband composite or s-video ntsc and pal signals, and convert them to either digital ycbcr or rgb data. in addition to performing the basic decoding operations, the HMP8115 includes hard- ware to decode different types of vbi data and to generate digital video patterns for a blue screen, black screen and full screen color bars. the digital plls are designed to synchronize to all ntsc and pal standards. a chroma pll is used to maintain chroma lock for demodulation of the color information; a line- locked pll is used to maintain vertical spatial alignment. the plls are designed to maintain lock even in the event of vcr headswitches and multipath noise. the HMP8115 contains two 8-bit a/d converters and an i 2 c interface for programming internal registers. external video processing before a video signal can be digitized the decoder has some external processing considerations that need to be addressed. this section discusses those external aspects of the HMP8115. analog video inputs the HMP8115 supports either three composite or two com- posite and one s-video input. three analog video inputs (ntsc/pal 1-3) are used to select which one of three composite video sources are to be decoded. to support s-video applications, the y channel drives the ntsc/pal 3 analog input, and the c channel drives the c analog input. the analog inputs must be ac-coupled to the video signals, as shown in the applications section. anti-aliasing filters an external anti-alias ?lter is required to achieve optimum performance and prevent high frequency components from being aliased back into the video image. for the ntsc/pal 1-3 inputs, a single ?lter is connected between the yout and yin pins. for the c input, the anti- aliasing ?lter should be connected before the c input. a rec- ommended ?lter is shown in figure 1. s-video chroma gain control the chroma portion of s-video is ac coupled through an anti-aliasing ?lter as shown in the applications section. unlike the composite/luma inputs, the automatic gain con- trol (agc) for the chroma portion of s-video is done digitally inside the decoder as determined by bits 7 and 6 of the color processing register 06 h . in addition to the inter- nal agc, the designer can also apply some gain to the chroma before it reaches the internal agc logic. this gain is controlled by pin 28. the voltage at this pin determines the gain of the chroma before it gets digitized by the chroma a/d with a typical gain performance as shown in figure 2. digitization of video prior to a/d conversion, the video signal is dc restored and gained to generate known video levels into the digital pro- cessing logic. this process is addressed in the agc and dc restoration section. after digitization, sample rate con- verters and a comb ?lter are used to perform color separa- tion and demodulation. a/d conversion video data is sampled at the clk2 frequency then pro- cessed by the input sample rate converter. the output levels of the adc after agc processing are: (m) ntsc (b, d, g, h, i, n c ) (m, n) pal pal white 224 213 black 76 64 blank 64 64 sync 0 0 agc and dc restoration the agc ampli?er attenuates or ampli?es the analog video signal to ensure that the sync tip level generates code 0. the difference from the ideal sync tip level of 0 is used to control the amount of attenuation or gain of the analog video signal. the capacitor on the lagc_cap pin is used to store the voltage which sets the gain level of the input video ampli?er. dc restoration positions the video signal such that the dc level of the back porch generates an average code 64. the back porch is sampled to determine the average value. the capacitor on the l_cap pin is used to store the voltage figure 1. recommended anti-aliasing filter r 1 332 r 2 4.02k c 2 82pf l 1 8.2 m h c 1 33pf yout yin 7 6 5 4 3 2 1 0 linear gain 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 control voltage on the gain_ctrl pin temperature = 25 o c v cc = 5v figure 2. chrominance amplifier gain HMP8115
6 which sets the dc offset level into the input video ampli?er. during the s-video mode of operation the capacitor on the c_cap pin performs the same function as the l_cap capacitor, except the chroma video ampli?ers dc offset is set so that the chroma a/d generates a code of 128 during the back porch. the internal timing windows for agc and dc restoration are show in figure 3. input signal detection it is assumed there is no video input if a horizontal sync is not detected for 16 consecutive lines. when no video has been detected, nominal video timing is generated for the previously detected or programmed standard. a maskable interrupt is included to ?ag when no video has been detected (bit 6 of the interrupt mask register 0f h ) allowing for blue/black/color bar output modes to be enabled if desired. the vertical sync interrupt can be used in determining when a video signal is present at the currently selected video mux input. bit 0 of register 0f h is used to enable vertical sync interrupts. vertical sync and field detection the vertical sync and ?eld detect circuit uses a low time counter to detect the vertical sync sequence in the video data stream. the low time counter accumulates the low time encountered during any sync pulse, including serration and equalization pulses. when the low time count exceeds the vertical sync detect threshold, vsync is asserted immedi- ately. field is asserted at the same time that vsync is asserted. field is asserted low for odd ?elds and high for even ?elds. field is determined from the location in the video line where vsync is detected. if vsync is detected in the ?rst half of the line, the ?eld is odd. if vsync is detected in the second half of a line, the ?eld is even. in the case of lost vertical sync or excessive noise that would prevent the detection of vertical sync, the field output will continue to toggle. lost vertical sync is declared if after 337 lines, a vertical sync period was not detected for 1 or 3 (selectable) successive ?elds as speci?ed by bit 2 of the genlock control register 04 h . when this occurs, the plls are initialized to the acquisition state. y/c separation a composite video signal has the luma (y) and chroma (c) information mixed in the same video signal. the y/c separa- tion process is responsible for separating the composite video signal into these two components. the HMP8115 uti- lizes a comb ?lter to minimize the artifacts that are associ- ated with the y/c separation process. input sample rate converter the input sample rate converter is used to convert video data sampled at the clk2 rate to a virtual 4xf sc sample rate for comb ?ltering and color demodulation. an interpolating ?lter is used to generate the 4xf sc samples as illustrated in figure 4. comb filter a 2-line comb ?lter, using a single line delay, is used to per- form part of the y/c separation process. during s-video operation, the y signal bypasses the comb ?lter; the c signal is processed by the comb ?lter since it is an integral part of the chroma demodulator. during pal operation, the chroma trap ?lter should also be enabled for improved performance. since a single line store is used, the chroma will normally have a half-line vertical offset from the luma data. this may be eliminated, vertically aligning the chroma and luma sam- ples, at the expense of vertical resolution of the luma. bit 0 of the output format register 02 h controls this option. chroma demodulation the output of the comb ?lter is further processed using a patented frequency domain transform to complete the y/c separation and demodulate the chromanance. demodulation is done at a virtual 4xf sc sample rate using the interpolated data samples to generate u and v data. the demodulation process decimates by 2 the u/v sample rate. output sample rate converter the output sample rate converter converts the y, u and v data from a virtual 4xf sc sample rate to the desired output sample rate (i.e., 13.5mhz). it also vertically aligns the sam- ples based on the horizontal sync information embedded in the digital video data stream. the output sample rate is determined by the selected video standard and whether figure 3. agc and dc restore internal timing video input agc dc restore time incoming video samples time resampled video 4xf sc figure 4. sample rate conversion HMP8115
7 square or rectangular pixels are output. the output format is 4:2:2 for all modes except the rgb modes which use a 4:4:4 output format. clk2 input note that the color subcarrier is derived from clk2. any jitter on clk2 will be transferred to the color subcarrier, resulting in color changes. thus, clk2 should be derived from a sta- ble clock source, such as a crystal. the use of a pll to gen- erate clk2 is not recommended. clk2 must have a 50ppm accuracy and at least a 60/40% duty cycle to ensure proper operation. the clk2 clock rate must be one of the following frequencies: 24.54mhz 27.00mhz 29.50mhz the frequency of clk2 must be 2x the desired output sam- ple rate. the values in table 1 below indicate the clk2 clock rate based on the video standard and pixel mode. the out- put sample rate for the given video standard and pixel mode is half the clk2 clock rate. digital processing of video once the luma and chroma have been separated the HMP8115 then performs programmable modi?cations (i.e. contrast, coring, color space conversions, color agc, etc.) to the decoded video signal. uv to cbcr conversion the baseband u and v signals are scaled and offset to gen- erate a nominal range of 16-240 for both the cb and cr data. digital color gain control there are four types of color gain control modes available: no gain control, automatic gain control, ?xed gain control, and freeze automatic gain control. if no gain control is selected, the amplitude of the color dif- ference signals (cbcr) is not modi?ed, regardless of varia- tions in the color burst amplitude. thus, a gain of 1x is always used for cb and cr. if automatic gain control is selected, the amplitude of the color difference signals (cbcr) is compensated for variations in the color burst amplitude. the burst amplitude is averaged with the two previous lines having a color burst to limit line- to-line variations. a gain of 0.5x to 4x is used for cb and cr. if ?xed gain control is selected, the amplitude of the color difference signals (cbcr) is multiplied by a constant, regard- less of variations in the color burst amplitude. the constant gain value is speci?ed by the color gain register 1c h .a gain of 0.5x to 4x is used for cb and cr. limiting the gain to 4x limits the amount of ampli?ed noise. if freeze automatic gain control is selected, the amplitude of the color difference signals (cbcr) is multiplied by a con- stant. this constant is the value the agc circuitry generated when the freeze automatic gain command was selected. color killer if enable color killer is selected, the color output is turned off when the running average of the color burst amplitude is below approximately 25% of nominal for four consecutive ?elds. when the running average of the color burst ampli- tude is above approximately 25% of nominal for four consec- utive ?elds, the color output is turned on. the color output is also turned off when excessive phase error of the chroma pll is present. if force color off is selected, color information is never present on the outputs. if force color on is selected, color information is present on the outputs regardless of the color burst amplitude or chroma pll phase error. y processing the black level is subtracted from the luminance data to remove sync and any blanking pedestal information. nega- tive values of y are supported at this point to allow proper decoding of below black luminance levels. scaling is done to position black at 8-bit code 0 and white at 8-bit code 219. a chroma trap ?lter may be used to remove any residual color subcarrier from the luminance data. the center fre- quency of the chroma trap is automatically determined from the video standard being decoded. the chroma trap should be disabled during s-video operation to maintain maximum luminance bandwidth. alternately, a 3mhz lowpass ?lter may be used to remove high-frequency y data. this may make a noisy image more pleasing to the user, although softer. coring of the high-frequency y data may be done to reduce low-level high frequency noise. coring of the y data may also be done to reduce low-level noise around black. this forces y data with the following val- ues to a value of 0: coring = 1: 1 coring = 2: 1, 2 coring = 3: 1, 2. 3 high-frequency components of the luminance signal may be peaked to control the sharpness of the image. maximum gain may be selected to occur at either 2.6mhz or the color table 1. video standard clock rate selection summary video format allowable clk2 frequencies (mhz) rectangular pixel mode square pixel mode (m) ntsc 27.00 24.54 (b, d, g, h, i, n) pal 27.00 29.50 (m) pal 27.00 24.54 (n c ) pal 27.00 29.50 HMP8115
8 subcarrier frequency. this may be used to make the dis- played image more pleasing to the user. it should not be used if the output video will be compressed, as the circuit introduces high-frequency components that will reduce the compression ratio. the brightness control adds or subtracts a user-speci?ed dc offset to the y data. the contrast control multiplies the y data by a user-speci?ed amount. these may be used to make the displayed image more pleasing to the user. finally, a value of 16 is added to generate a nominal range of 16 (black) to 235 (white). cbcr processing the cbcr data is lowpass ?ltered to either 0.85 or 1.5mhz. coring of the cbcr data may be done to reduce low-level noise around zero. this forces cbcr data with the following values to a value of 128. coring = 1: 127, 129 coring = 2: 126, 127, 129, 130 coring = 3: 125, 126, 127, 129, 130, 131 the saturation control multiplies the cbcr data by a user- speci?ed amount. this may be used to make the displayed image more pleasing to the user. the cbcr data may also be optionally multiplied by the contrast value to avoid color shifts when changing contrast. the hue control provides a user-speci?ed phase offset to the color subcarrier during decoding. this may be used to cor- rect slight hue errors due to transmission. ycbcr output format processing y has a nominal range of 16 to 235. cb and cr have a nomi- nal range of 16 to 240, with 128 corresponding to zero. val- ues less than 1 are made 1 and values greater than 254 are made 254. while blank is asserted, y is forced to have a value of 16, with cb and cr forced to have a value of 128, unless vbi data is present. rgb output format processing the 4:2:2 ycbcr data is converted to 4:4:4 ycbcr data and then converted to either 15-bit or 16-bit gamma-corrected rgb (r g b ) data. while blank is asserted, rgb data is forced to a value of 0. 15-bit r g b the following ycbcr to r g b equations are used to main- tain the proper black and white levels: r = 0.142(y - 16) + 0.194(cr - 128) g = 0.142(y - 16) - 0.099(cr - 128) - 0.048(cb - 128) b = 0.142(y - 16) + 0.245(cb - 128) the resulting 15-bit r g b data has a range of 0 to 31. val- ues less than 0 are made 0 and values greater than 31 are made 31. the 15-bit r g b data may be converted to 15-bit linear rgb, using the following equations. although the pal speci- ?cations specify a gamma of 2.8, a gamma of 2.2 is normally used. the HMP8115 allows the selection of the gamma to be either 2.2 or 2.8, independent of the video standard. for gamma = 2.2: for r g b < 0.0812*31 r = (31)((r /31)/4.5) g = (31)((g /31)/4.5) b = (31)((b /31)/4.5) for r g b >= 0.0812*31 r = (31)(((r /31) + 0.099)/1.099) 2.2 g = (31)(((g /31) + 0.099)/1.099) 2.2 b = (31)(((b /31) + 0.099)/1.099) 2.2 for gamma = 2.8: r = (31)(r /31) 2.8 g = (31)(g /31) 2.8 b = (31)(b /31) 2.8 16-bit r g b the following ycbcr to r g b equations are used to main- tain the proper black and white levels: r = 0.142(y - 16) + 0.194(cr - 128) g = 0.288(y - 16) - 0.201(cr - 128) - 0.097(cb - 128) b = 0.142(y - 16) + 0.245(cb - 128) the resulting 16-bit r g b data has a range of 0 to 31 for r and b , and a range of 0 to 63 for g . values less than 0 are made 0; r and b values greater than 31 are made 31, g values greater than 63 are made 63. the 16-bit r g b data may be converted to 16-bit linear rgb, using the following equations. although the pal speci- ?cations specify a gamma of 2.8, a gamma of 2.2 is normally used. the HMP8115 allows the selection of the gamma to be either 2.2 or 2.8, independent of the video standard. for gamma = 2.2: for r b < 0.0812*31, g < 0.0812*63 r = (31)((r /31)/4.5) g = (63)((g /63)/4.5) b = (31)((b /31)/4.5) for r b >= 0.0812*31, g >= 0.0812*63 r = (31)(((r /31) + 0.099)/1.099) 2.2 g = (63)(((g /63) + 0.099)/1.099) 2.2 b = (31)(((b /31) + 0.099)/1.099) 2.2 for gamma = 2.8: r = (31)(r /31) 2.8 g = (63)(g /63) 2.8 b = (31)(b /31) 2.8 HMP8115
9 built-in video generation when the blue screen, black screen or color bar output is selected, a full-screen of blue, black or 75% colorbar output is generated using the currently selected output format. the type of screen to be generated is determined by bits 2 and 1 of the output format register 02 h . when built-in video generation is not desired, the bits need to be set for normal operation to pass decoded video. if a video source is input, it will be used to provide the video timing. if an input video source is not detected, internally- generated video timing will be used. pixel port timing the the timing and format of the output data and control sig- nals is presented in the following sections. hsync and vsync timing the hsync and vsync output timing is vmi v1.4 compati- ble. figures 5-8 illustrate the video timing. the leading edge of hsync is synchronous to the video input signal and has a ?xed latency due to internal pipeline processing. the pulse width of the hsync is de?ned by the end hsync register 36h, where the trailing edge of hsync has a programmable delay of 0-510 clk2 cycles from the leading edge. the leading edge of vsync is asserted approximately half way through the ?rst serration pulse of each ?eld. for an odd ?eld, the trailing edge of vsync is 5 1 clk2 cycles after the trailing edge of the hsync that follows the last equaliza- tion pulse. refer to figures 5 and 7. for an even ?eld, the trailing edge of vsync is 5 1 clk2 cycles leading the lead- ing edge of the hsync that follows the last equalization pulse. refer to figures 6 and 8. field timing when ?eld information can be determined from the input video source, the field output pin re?ects the video source ?eld state. when ?eld information cannot be determined from the input video source, the field output pin alternates its state at the beginning of each ?eld. field changes state 5 1 clk2 cycles before the leading edge of vsync. video vsync field even field note: 3. the trailing edge of vsync is 5 1 clocks after the trailing edge of hsync to be vmi compatible and to indicate a transition to an odd field. figure 5. ntsc(m) and pal(m) hsync, vsync and field timing during an even to odd field transition odd field hsync input 523 pal(m) 5245251234567 522 521 1 ntsc(m) 2345678910 525 524 line # line # note: 4. the trailing edge of vsync is 5 1 clocks after the leading edge of hsync to be vmi compatible and to indicate a transition to an even field. figure 6. ntsc(m) and pal(m) hsync, vsync and field timing during an odd to even field transition video vsync field odd field even field hsync input 261 pal(m) 262 263 264 265 266 267 268 269 270 260 259 264 ntsc(m) 265 266 267 268 269 270 271 272 273 263 262 line # line # HMP8115
10 blank and d v alid timing d v alid is asserted when p15-p0 contain valid data. the timing and behavior of d v alid is dependent on the output video format and the programmed values for bit 4 (dvld_dcyc) and bit 5 (dvld_ltc) of the genlock control register 04 h . refer to the speci?c output video format sections that follow for the speci?c behavior for d v alid. blank is used to determine if the HMP8115 is generating active video data. blank should be used in conjunction with d v alid to capture digital data from the decoder. blank, d v alid and the video data are output after the internal pipe- line latency and synchronous with the rising edge of clk2. during active scan lines blank is negated when the hori- zontal pixel count matches the value in the end h_blank register 32 h . a count of 00 h corresponds to the 50% point of the leading edge of the sync tip after leaving the part. blank is asserted when the horizontal pixel count matches the value in the start h_blank register 31 h /30 h . note that horizon- tally, blank is programmable with two pixel resolution. start v_blank register 34 h /33 h and end v_blank reg- ister 35 h determine which scan lines are blanked for each ?eld. during inactive scan lines, blank is asserted during the entire scan line. half-line blanking of the output video cannot be done. reference figure 9 for active video timing and use table 2 for typical blanking programming values. video vsync field even field note: 5. the trailing edge of vsync is 5 1 clocks after the trailing edge of hsync is to be vmi compatible and to indicate a transition to an odd field. figure 7. pal(b,d,g,h,i,n,n c ) hsync, vsync and field timing during an even to odd field transition odd field hsync input 623 line # 6246251234567 622 621 note: 6. the trailing edge of vsync is 5 1 clocks after the leading edge of hsync to be vmi compatible and to indicate a transition to an even field. figure 8. pal(b,d,g,h,i,n,n c ) hsync, vsync and field timing during an odd to even field transition video vsync field odd field even field hsync input 311 line # 312 313 314 315 316 317 318 319 320 310 309 table 2. typical values for hblank and vblank registers video standard (msb/lsb) active pixels/ line total pixels/ line last pixel count start h_blank (31h/30h) end h_blank (32h) start v_blank (34h/33h) end v_blank (35h) rectangular pixels ntsc (m), pal (m) pal (b, d, g, h, i,n, n c ) 720 720 858 864 857 (0359 h ) 863 (035f h ) 842 (034a h ) 852 (0354 h ) 122 (7a h ) 132 (84 h ) 259 (0103 h ) 310 (0136 h ) 19 (13 h ) 22 (16 h ) square pixels ntsc (m), pal (m) pal (b, d, g, h, i,n, n c ) 640 768 780 944 779 (030b h ) 943 (03af h ) 758 (02f6 h ) 922 (039a h ) 118 (76 h ) 154 (9a h ) 259 (0103 h ) 310 (0136 h ) 19 (13 h ) 22 (16 h ) HMP8115
11 pixel output port pixel data is output via the p0-p15 pins. refer to table 3 for the output pin de?nition as a function of the output mode. 8-bit ycbcr output the d v alid output pin may be con?gured to operate in one of two ways. the con?guration is determined by the dvld_ltc bit (bit 4) of the genlock control register 04 h . if dvld_ltc=0, the d v alid output is continuously asserted during the entire active video time on active scan lines if clk2 is exactly 2x the desired output sample rate. d v alid being asserted indicates valid pixel data is present on the p15-p8 pixel outputs. d v alid is never asserted during the blanking intervals. refer to figure 10. if dlvd_ltc=1, d v alid has the same internal timing as the ?rst mode, but is anded with the clk2 signal, and the result is output onto the d v alid pin. this results in a gated clk2 signal being output during the active video time on active scan lines. refer to figure 11. if 8-bit ycbcr data is generated, it is output following each rising edge of clk2. the ycbcr data is multiplexed as [cb y cr y cbycry ...], with the ?rst active data each scan line containing cb data. the pixel output timing is shown in fig- ures 10 and 11. blank, hsync, vsync, d v alid, vbiv alid, and field are output following the rising edge of clk2. when blank is asserted and vbiv alid is deasserted, the ycbcr outputs have a value of 16 for y and 128 for cb and cr. note: 7. the line numbering for pal (m) followings ntsc (m) line count minus 3 per the video standards. figure 9. typical active video regions lines 1 - 22 not active ntsc m pal b, d, g, h, i, n, n c odd field lines 263 - 284 not active even field lines 1 - 22 not active lines 311 - 335 not active 858 number of pixels total pixels active pixels 720 (780) (640) 864 total pixels active pixels 720 (944) (768) rectangular (square) sync and back porch front porch vertical blanking ntsc pal 480 active lines/frame (ntsc, pal m) 576 active lines/frame (pal) (lines 23-262) 240 active lines per field (lines 285 - 524) 240 active lines per field line 525 not active (lines 23 - 310) 288 active lines per field lines 624-625 not active (lines 336 - 623) 288 active lines per field table 3. pixel output formats pin name 8-bit, 4:2:2, ycbcr 16-bit, 4:2:2, ycbcr 15-bit, rgb, (5,5,5) 16-bit, rgb, (5,6,5) bt.656 p0 p1 p2 p3 p4 p5 p6 p7 0 0 0 0 0 0 0 0 cb0, cr0 cb1, cr1 cb2, cr2 cb3, cr3 cb4, cr4 cb5, cr5 cb6, cr6 cb7, cr7 b0 b1 b2 b3 b4 g0 g1 g2 b0 b1 b2 b3 b4 g0 g1 g2 0 0 0 0 0 0 0 0 p8 p9 p10 p11 p12 p13 p14 p15 y0, cb0, cr0 y1, cb1, cr1 y2, cb2, cr2 y3, cb3, cr3 y4, cb4, cr4 y5, cb5, cr5 y6, cb6, cr6 y7, cb7, cr7 y0 y1 y2 y3 y4 y5 y6 y7 g3 g4 r0 r1 r2 r3 r4 0 g3 g4 g5 r0 r1 r2 r3 r4 ycbcr data, ancillary data, sav and eav sequences HMP8115
12 16-bit ycbcr, 15-bit rgb, or 16-rgb output in these output modes, d v alid may be con?gured to oper- ate in one of four modes as controlled by the dvld_ltc and dvld_dcyc bits of the genlock control register (04 h ). bit 4 is the dvld_ltc bit and bit 5 is the dvld_dcyc bit. if dvld_ltc=0 and dvld_dcyc=0, d v alid is present only during the active video time on active scan lines. thus, d v alid being asserted indicates valid pixel data is present on the p0-p15 pixel outputs. d v alid is never asserted dur- ing the blanking intervals. in this mode d v alid will have a 50% duty cycle only during the active video times. the tim- ing diagrams for this mode can be found in figures 12 and 13. if dvld_ltc=0 and dvld_dcyc=1, d v alid behaves the same as the ?rst mode, with the exception that d v alid does not have a 50% duty cycle. this mode is intended for back- ward compatibility with hmp8112(a) timing dependencies in which d v alid did not have a 50% duty cycle timing and other timing variations. the timing diagrams for this mode can be found in figures 14 and 15. if dvld_ltc=1 and dvld_dcyc=0, d v alid is present the entire line time on all scan lines. d v alid may occasionally be negated for two consecutive clk2 cycles just prior to active video. in this mode d v alid is guaranteed have a 50% duty cycle only during the active video times. the timing for this mode differs from the timing shown in figures 12 and 13 only in that d v alid will also be asserted during the blanking portion of the video line time as described above. if dvld_ltc=1 and dvld_dcyc=1, d v alid is present during the entire line time on all scan lines. d v alid is asserted during the blanking intervals as needed to ensure a constant number of total samples per line. the timing for this mode differs from the timing shown in figures 14 and 15 only in that d v alid will also be asserted during the blanking portion of the video line time as described above. note: 8. y 0 is the first active luminance pixel data of a line. cb 0 and cr 0 are first active chrominance pixel data in a line. cb and cr will alternate every cycle due to the 4:2:2 subsampling. pixel data is not output during the blanking period, but the values on the ports are forced to blanking levels. figure 10. output timing for 8-bit ycbcr mode (dvld_ltc = 0) clk d v alid p[15-8] t dvld cb 0 y 0 cr 0 cb 2 y 2 cr 2 y 1 y 3 cb 4 y 4 blank clk d v alid p[15-8] t dvld cb 0 y 0 cr 0 cb 2 y 2 cr 2 y 1 y 3 cb 4 notes: 9. y 0 is the first active luminance pixel data of a line. cb 0 and cr 0 are first active chrominance pixel data in a line. cb and cr will alternate every cycle due to the 4:2:2 subsampling. pixel data is not output during the blanking period, but the values on the ports are forced to blanking levels. 10. when dvld_ltc is set to 1, the polarity of d v alid needs to be set to active low, otherwise d v alid will stay low during active video and be gated with the clock only during the blanking interval. figure 11. output timing for 8-bit ycbcr mode (dvld_ltc = 1) y 4 blank HMP8115
13 if 16-bit ycbcr, 15-bit rgb data, or 16-bit rgb data is gen- erated, it is output following the rising edge of clk2 while d v alid is asserted. either linear or gamma-corrected rgb data may be output. the pixel output timing is shown in fig- ures 12 to 15. blank, hsync, vsync, d v alid, vbiv alid, and field are output following the rising edge of clk2. when blank is asserted and vbiv alid is deasserted, the ycbcr outputs have a value of 16 for y and 128 for cb and cr; the rgb out- puts have a value of 0. notes: 11. y 0 is the first active luminance pixel data of a line. cb 0 and cr 0 are first active chrominance pixel data in a line. cb and cr will alternate every cycle due to the 4:2:2 subsampling. 12. blank is asserted per figure 9. figure 12. output timing for 16-bit ycbcr mode (dvld_ltc = 0, dvld_dcyc = 0) y 0 cb 0 clk d v alid blank p15-p8 p7-p0 t dvld y 1 y 2 y 3 y 4 cr 0 cb 2 cr 2 cb 4 note: 13. blank is asserted per figure 9. figure 13. output timing for 16-bit [15-bit] rgb mode (dvld_ltc = 0, dvld_dcyc = 0) r 0 g 0 clk d v alid p15-p11 p10-p5 t dvld r 1 r 2 r 3 r 4 g 1 g 2 g 3 g 4 b 0 p4-p0 b 1 b 2 b 3 b 4 [p9-p5] [p14-p10] HMP8115
14 8-bit bt.656 output if bt.656 data is generated, it is output following each rising edge of clk2. the bt.656 eav and sav formats are shown in table 4 and the pixel output timing is shown in figure 16. the eav and sav timing is determined by the programmed horizontal and vertical blank timing blank, hsync, vsync, d v alid, vbiv alid, and field are output following the rising edge of clk2. for proper operation, clk2 must be exactly 2x the desired output sample rate. the d v alid output is continuously asserted during the entire active video time. during the blanking intervals, the ycbcr outputs have a value of 16 for y and 128 for cb and cr, unless ancillary data is present. due to the use of digital plls and source video timing the total # of samples per line may not equal exactly 1716 (ntsc) or 1728 (pal). the active video portion of the bt.656 data stream is always exactly 1440 continuous sam- ples. any line-to-line timing difference from nominal # of samples per line, plus or minus, is accommodated in the hor- izontal blanking interval. notes: 14. y 0 is the first active luminance pixel of a line. cb 0 and cr 0 are first active chrominance pixels in a line. cb and cr will alternate every cycle due to the 4:2:2 subsampling. 15. blank is asserted per figure 9. 16. d v alid is asserted for every valid pixel during both active and blanking regions. d v alid is not a 50% duty cycle synchronous output and will appear to jitter as the output sample rate converter adjusts the output timing for various data rates and clock frequency inputs. figure 14. output timing for 16-bit ycbcr mode (dvld_ltc = 0, dvld_dcyc = 1) y 0 cb 0 y 1 cr 0 y 2 cb 2 y 3 cr 2 y 4 cb 4 clk d v alid p15-p8 p7-p0 t dvld notes: 17. blank is asserted per figure 9. 18. d a vlid is asserted for every valid pixel during both active and blanking regions. d v alid is not a 50% duty cycle synchronous output and will appear to jitter as the output sample rate converter adjusts the output timing for various data rates and clock frequency inputs. figure 15. output timing for 16-bit [15-bit] rgb mode (dvld_ltc = 0, dvld_dcyc = 1) r0 g 0 r 1 g 0 r 2 g 2 r 3 g 2 r 4 g 4 clk d v alid blank t dvld b 0 b 1 b 2 b 3 b 4 p15-p11 p10-p5 p4-p0 [p9-p5] [p14-p10] HMP8115
15 . advanced features in addition to digitizing an analog video signal the HMP8115 has hardware to process different types of vertical blanking interval (vbi) data as described in the following sections. sliced vbi data capture the HMP8115 implements sliced data capture of select types of vbi data. the vbi decoders incorporate detection hysteresis to prevent them from rapidly turning on and off due to noise and transmission errors. in order to handle real- world signals, the vbi decoders also compensate for dc off- sets and amplitude variations. closed captioning during closed captioning capture, the scan lines containing captioning information are monitored. if closed captioning is enabled and captioning data is present, the caption data is loaded into the caption data registers. detection of closed captioning the closed caption decoder monitors the appropriate scan lines looking for the clock run-in and start bits used by cap- tioning. if found, it locks to the clock run-in, the caption data is sampled and loaded into shift registers, and the data is then transferred to the caption data registers. if the clock run-in and start bits are not found, it is assumed the scan line contains video data unless other vbi informa- tion is detected, such as teletext. once the clock run-in and start bits are found on the appro- priate scan line for four consecutive odd ?elds, the closed captioning odd ?eld detect status bit is set to 1. it is reset to 0 when the clock run-in and start bits are not found on the appropriate scan lines for four consecutive odd ?elds. once the clock run-in and start bits are found on the appro- priate scan line for four consecutive even ?elds, the closed captioning even ?eld detect status bit is set to 1. it is reset to 0 when the clock run-in and start bits are not found on the appropriate scan lines for four consecutive even ?elds. clk d v alid blank p[15-8] t dvld ff 00 00 cb 0 y 0 cr 0 status y 1 cb 2 notes: 19. y 0 is the first active luminance pixel data of a line. cb 0 and cr 0 are first active chrominance pixel data in a line. cb and cr will alternate every cycle due to the 4:2:2 subsampling. pixel data is not output during the blanking period. 20. notice that d v alid is not asserted during the preamble and that blank is still asserted. 21. see table 4 for status bit definitions. figure 16. output timing for 8-bit bt.656 mode y 2 table 4. bt.656 eav and sav sequences pixel input p15 p14 p13 p12 p11 p10 p9 p8 preamble 11111111 00000000 00000000 status word 1 f v h p3 p2 p1 p0 notes: 22. p3 = v xor h; p2 = f xor h; p1 = f xor v; p0 = f xor v xor h 23. f: 0 = field 1; 1 = field 2 24. v: 1 during vertical blanking 25. h: 0 at sav (start of active video); 1 at eav (end of active video) HMP8115
16 reading the caption data the caption data registers may be accessed in two ways: via the i 2 c interface or as bt.656 ancillary data. captioning disabled on both lines in this case, any caption data present is ignored. the caption odd ?eld read status bit and the caption even ?eld read status bit are always a 0. odd field captioning in this case, any caption data present on line 284 (or line 281 or 335 in the pal modes) is ignored. caption data present on line 21 (or line 18 or 22 in the pal modes) is captured into a shift register then transferred to closed caption_odd_a register 20 h and closed caption_odd_b register 21 h . the caption even field read status bit is always a 0. the caption odd field read status bit is set to 1 after data has been transferred from the shift register to the closed caption_odd_a and closed caption_odd_b regis- ters. it is set to 0 after the data has been read out. even field captioning in this case, any caption data present on line 21 (or line 18 or 22 in the pal modes) is ignored. caption data present on line 284 (or line 281 or 335 in the pal modes) is captured into a shift register then transferred to closed caption_even_a register 22 h and closed caption_even_b register 23 h . the caption odd ?eld read status bit is always a 0. the caption even ?eld read status bit is set to 1 after data has been transferred from the shift register to the closed caption_even_a and closed caption_even_b reg- isters. it is set to 0 after the data has been read out. odd and even field captioning caption data present on line 21 (or line 18 or 22 in the pal modes) is captured into a shift register then transferred to the closed caption_odd_a and closed caption_odd_b registers. caption data present on line 284 (or line 281 or 335 in the pal modes) is captured into a shift register then transferred to the closed caption_even_a and closed caption_even_b registers. the caption odd ?eld read status bit is set to 1 after data has been transferred from the shift register to the closed caption_odd_a and closed caption_odd_b regis- ters. it is set to 0 after the data has been read out. the caption even ?eld read status bit is set to 1 after data has been transferred from the shift register to the closed caption_even_a and closed caption_even_b reg- isters. it is set to 0 after the data has been read out. widescreen signalling (wss) during wss capture (itu-r bt.1119 and eiaj cpx-1204), the scan lines containing wss information are monitored. if wss is enabled and wss data is present, the wss data is loaded into the wss data registers. detection of wss the wss decoder monitors the appropriate scan lines look- ing for the run-in and start codes used by wss. if found, it locks to the run-in code, the wss data is sampled and loaded into shift registers, and the data is then transferred to the wss data registers. if the run-in and start codes are not found, it is assumed the scan line contains video data unless other vbi information is detected, such as teletext. once the run-in and start codes are found on the appropriate scan line for four consecutive odd ?elds, the wss line 20 detect status bit is set to 1. it is reset to 0 when the run-in and start codes are not found on the appropriate scan lines for four consecutive odd ?elds. once the run-in and start codes are found on the appropriate scan line for four consecutive even ?elds, the wss line 283 detect status bit is set to 1. it is reset to 0 when the clock run-in and start bits are not found on the appropriate scan lines for four consecutive even ?elds. reading the wss data the wss data registers may be accessed in two ways: via the i 2 c interface or as bt.656 ancillary data. wss disabled on both lines in this case, any wss data present is ignored. the wss odd ?eld read status bit and the wss even ?eld read status bit are always a 0. odd field wss in this case, any wss data present on line 283 (or line 280 or 336 in the pal modes) is ignored. wss data present on line 20 (or line 17 or 23 in the pal modes) is captured into a shift register then transferred to the wss_odd_a and wss_odd_b data registers. the wss even ?eld read status bit is always a 0. the wss odd ?eld read status bit is set to 1 after data has been transferred from the shift register to the wss_odd_a and wss_odd_b registers. it is set to 0 after the data has been read out. even field wss in this case, any wss data present on line 20 (or line 17 or 23 in the pal modes) is ignored. wss data present on line 283 (or line 280 or 336 in the pal modes) is captured into a shift register then transferred to the wss_even_a and wss_even_b data registers. the wss odd ?eld read status bit is always a 0. the wss even ?eld read status bit is set to 1 after data has been transferred from the shift register to the wss_even_a and wss_even_b registers. it is set to 0 after the data has been read out. HMP8115
17 odd and even wss wss data present on line 20 (or line 17 or 23 in the pal modes) is captured into a shift register then transferred to the wss_odd_a and wss_odd_b registers. wss data present on line 283 (or line 280 or 336 in the pal modes) is captured into a shift register then transferred to the wss_even_a and wss_even_b registers. the wss odd ?eld read status bit is set to 1 after data has been transferred from the shift register to the wss_odd_a and wss_odd_b registers. it is set to 0 after the data has been read out. the wss even ?eld read status bit is set to 1 after data has been transferred from the shift register to the wss_even_a and wss_even_b registers. it is set to 0 after the data has been read out. bt.656 ancillary data through the bt.656 interface the HMP8115 can generate non-active video data which contains cc, wss, teletext or real-time control interface (rtci) information. teletext and rtci data is only available as bt.656 ancillary data. vbiv alid output timing the vbiv alid output is asserted when outputting closed captioning, widescreen signalling, teletext or rtci data as bt.656 ancillary data. it is asserted during the entire bt.656 ancillary data packet time, including the preamble. bt.656 closed captioning and wide screen signalling table 5 illustrates the format when outputting the caption data registers as bt.656 ancillary data. the ancillary data is present during the horizontal blanking interval after the line containing the captioning information. table 6 illustrates the format when outputting the wss data registers as bt.656 ancillary data. the ancillary data is present during the horizontal blanking interval after the line containing the wss information. clk vbiv alid p[15-8] t dvld 00 ff ff blk # # bytes/4 byte #1 data id notes: 26. bt.656 vbi ancillary starts with a 00h, ffh and ffh sequence which is opposite to the sav/eav sequence of ffh, 00h and 00h. 27. during active vbi data intervals, d v alid is deasserted and blank is asserted. figure 17. output timing for bt.656 vbi data transfers (cc, wss, teletext, rtci) byte #2 byte #3 byte #4 table 5. reading the closed caption data as bt.656 ancillary data pixel output p15 p14 p13 p12 p11 p10 p9 p8 preamble 0 000000 0 1111111 1 1111111 1 data id p14ep110000 = odd field data 1 = even field data data block number p14ep00000 1 data word count p14ep00000 1 caption data p14 ep 0 0 bit 15 bit 14 bit 13 bit 12 p14 ep 0 0 bit 11 bit 10 bit 9 bit 8 p14 ep 0 0 bit 7 bit 6 bit 5 bit 4 p14 ep 0 0 bit 3 bit 2 bit 1 bit 0 crc p14 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 notes: 28. ep = even parity for p8-p13. 29. crc = sum of p8-p14 of data id through last user data word. preset to all zeros, carry is ignored. HMP8115
18 teletext the HMP8115 supports itu-r bt.653 625-line and 525-line teletext system b, c and d capture. nabts (north american broadcast teletext speci?cation) is the same as bt.653 525- line system c, which is also used to transmit intel intercast? information. wst (world system teletext) is the same as bt.653 system b. figure 18 shows the basic structure of a video signal that contains teletext data. the scan lines containing teletext information are monitored. if teletext is enabled and teletext data is present, the teletext data is output as bt.656 ancillary data. detection of teletext the teletext decoder monitors the scan lines, looking for the 16-bit clock run-in (sometimes referred to as the clock syn- chronization code) used by teletext. if found, it locks to the clock run-in, the teletext data is sampled and loaded into shift registers, and the data is then transferred to internal holding registers. if the clock run-in is not found, it is assumed the scan line contains video data unless other vbi information is detected, such as wss. if a teletext clock run-in is found before line 23 or line 289 for ntsc and (m) pal, or line 336 for (b, d, g, h, i, n, n c ) pal, the vbi teletext detect status bit is immediately set to 1. if not found by these lines, the status bit is immediately reset to 0. accessing the teletext data the teletext data must be output as bt.656 ancillary data. the i 2 c interface does not have the bandwidth to output teletext information when needed. table 7 illustrates the teletext bt.656 ancillary data format and figure 17 depicts the portion of the incoming teletext signal which is sliced and output as part of the ancillary data stream. the teletext data is present during the horizontal blanking interval after the line containing the teletext infor- mation. the actual bt.656 bytes that contain teletext data only contain 4 bits of the actual data packet. note that only the data packet of figure 18 is sent as ancillary data; the clock run-in is not included in the data stream. table 6. outputting the sliced wss data as bt.656 ancillary data pixel output p15 p14 p13 p12 p11 p10 p9 p8 preamble 0 0 0 0 0 0 0 0 1111111 1 1111111 1 data id p14 ep 1 1 0 0 1 0 =odd field data 1 =even field data data block number p14 ep 0 0 0 0 0 1 data word count p14 ep 0 0 0 0 1 0 wss data p14 ep 0 0 0 0 bit 13 bit 12 p14 ep 0 0 bit 11 bit 10 bit 9 bit 8 p14 ep 0 0 bit 7 bit 6 bit 5 bit 4 p14 ep 0 0 bit 3 bit 2 bit 1 bit 0 wss crc data p14 ep 0 0 0 0 bit 5 bit 4 p14 ep 0 0 bit 3 bit 2 bit 1 bit 0 p14 ep 0 0 0 0 0 0 p14 ep 0 0 0 0 0 0 crc p14 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 notes: 30. ep = even parity for p8-p13. 31. wss crc data = 00 0000 during pal operation. 32. crc = sum of p8-p14 of data id through last user data word. preset to all zeros, carry is ignored. HMP8115 intercast? is a trademark of intel corporation.
19 notes: 33. the msb is bit number: 271 for system c, 279 for system b 525-line and 343 for system b 625-line. 34. the clock run-in is 16 bits wide for both systems and is not included in the bt.656 ancillary data stream. 35. the bit rate is 5.727272 mbits/second for system b and c on 525/60 systems and 6.9375 and 5.734375 mbits/second respectively for 625/50 systems. figure 18. teletext vbi video signal data packet clock run-in bit 0 msb table 7. outputting the sliced teletext data as bt.656 ancillary data pixel input p15 p14 p13 p12 p11 p10 p9 p8 preamble 0 0 0 0 0000 1 1 1 1 1111 1 1 1 1 1111 data id p14ep 1 1 0100 data block number p14ep 0 0 0001 data word count p14ep 0 1 0110 teletext data (b, 625-line = 43 bytes) (b, 525-line = 35 bytes) (c = 34 bytes) p14 ep 0 = 525-line 1 = 625-line 0 = system b 1 = system c bit 343 bit 342 bit 341 bit 340 p14 ep 0 0 bit 339 bit 338 bit 337 bit 336 : p14 ep 0 0 bit 7 bit 6 bit 5 bit 4 p14 ep 0 0 bit 3 bit 2 bit 1 bit 0 reserved p14ep 0 0 0000 p14ep 0 0 0000 crc p14 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 notes: 36. ep = even parity for p8-p13. 37. crc = sum of p8-p14 of data id through last user data word. preset to all zeros, carry is ignored. 38. for 525-line system b, bits 280-343 are 0. 39. for system c, bits 272-343 are 0. HMP8115
20 real time control interface the real time control interface (rtci) outputs timing infor- mation for a ntsc/pal encoder as bt.656 ancillary data. this allows the encoder to generate clean output video. rtci information via bt.656 ancillary data is shown in table 8. if enabled, this transfer occurs once per line and is com- pleted before the start of the sav sequence. the psw bit is always a 0 for ntsc encoding. during pal encoding, it indicates the sign of v (0 = negative; 1 = pos- itive) for that scan line. table 8. outputting rtci as bt.656 ancillary data pixel input p15 p14 p13 p12 p11 p10 p9 p8 preamble 0 0 0 0 0 0 0 0 1 1111111 1 1111111 data id p14 ep 1 1 0 1 0 1 data block number p14 ep 0 0 0 0 0 1 data word count p14 ep 0 0 0 0 1 1 hpll increment p14 ep 0 0 0 0 0 0 p14 ep 0 0 0 0 0 0 p14 ep 0 0 0 0 0 0 p14 ep 0 0 0 0 0 0 fscpll increment p14 ep psw 0 bit 31 bit 30 bit 29 bit 28 p14 ep f2 = 0 f1 = 0 bit 27 bit 26 bit 25 bit 24 : p14 ep 0 0 bit 7 bit 6 bit 5 bit 4 p14 ep 0 0 bit 3 bit 2 bit 1 bit 0 crc p14 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 notes: 40. ep = even parity for p8-p13. 41. crc = sum of p8-p14 of data id through last user data word. preset to all zeros, carry is ignored. HMP8115
21 host interface all internal registers may be written to or read by the host processor at any time, except for those bits identi?ed as read-only. the bit descriptions of the control registers are listed in tables 9-48. the HMP8115 supports the fast-mode (up to 400 kbps) i 2 c interface consisting of the sda and scl pins. the device acts as a slave for receiving and transmitting data over the serial interface. when the interface is not active, scl and sda must be pulled high using external 4k w pull-up resis- tors. the slave address for the HMP8115 is 88 h . data is placed on the sda line when the scl line is low and held stable when the scl line is pulled high. changing the state of the sda line while scl is high will be interpreted as either an i 2 c bus start or stop condition as indicated by figure 20. during i 2 c write cycles, the ?rst data byte after the slave address is treated as the control register sub address and is written into the internal address register. any remaining data bytes sent during an i 2 c write cycle are written to the control registers, beginning with the register speci?ed by the address register as given in the ?rst byte. the address regis- ter is then autoincremented after each additional data byte sent on the i 2 c bus during a write cycle. writes to reserved bits within registers or reserved registers are ignored. in order to perform a read from a speci?c control register within the HMP8115, an i 2 c bus write must ?rst be per- formed to properly setup the address register. then an i 2 c bus read can be performed to read from the desired control register(s). as a result of needing the write cycle for a read cycle there are actually two start conditions as shown in figure 21. the address register is then autoincremented after each byte read during the i 2 c read cycle. reserved registers return a value of 00 h . figure 19. i 2 c timing diagram sda scl t buf t low t high t r t f t su:data t hd:data t su:stop sda scl start condition s 1-7 address 8 r/w 9 ack 1-7 data 89 ack stop condition p figure 20. i 2 c serial data flow s = start cycle p = stop cycle a = acknowledge from master from HMP8115 0x88 data write data data 0x88 data read na = no acknowledge 0x89 1000 1000 (r/w) 1000 1000 figure 21. register write/read flow s chip addr a sub addr data data p na chip addr s sub addr chip addr s p a a a a a a register pointed to by sub addr optional frame may be repeated n times a register pointed to by sub addr optional frame may be repeated n times HMP8115
22 HMP8115 control registers table 9. 8115 register summary sub- address control register reset/ default value use value comments 00 h product id 15 h 01 h input format 18 h defaults to autodetect of input video standard 02 h output format 00 h defaults to 16-bit ycbcr format 03 h output control 00 h defaults to outputs disabled 04 h genlock control 01 h defaults to 27mhz clk2, rectangular pixel mode 05 h analog input control 00 h defaults to input signal select = ntsc/pal1 06 h color processing 52 h 07 h reserved - 08 h luma processing 04 h 09 h reserved - 0a h sliced vbi data enable 00 h 0b h sliced vbi data output 00 h 0c h vbi data status 00 h 0d h reserved - 0e h video status 00 h 0f h interrupt mask 00 h 10 h interrupt status 00 h 11 h -17 h reserved - 18 h brightness 00 h 19 h contrast 80 h 1a h hue 00 h 1b h saturation 80 h 1c h color gain 40 h 1d h reserved - 1e h sharpness 10 h 1f h host control 00 h 20 h closed caption_odd_a 80 h 21 h closed caption_odd_b 80 h 22 h closed caption_even_a 80 h 23 h closed caption_even_b 80 h 24 h wss_odd_a 00 h 25 h wss_odd_b 00 h 26 h wss_crc_odd 00 h 27 h wss_even_a 00 h 28 h wss_even_b 00 h 29 h wss_crc_even 00 h 2a h -2f h reserved - HMP8115
23 30 h start h_blank low 4a h table 2 31 h start h_blank high 03 h table 2 32 h end h_blank 7a h table 2 33 h start v_blank low 02 h table 2 34 h start v_blank high 01 h table 2 35 h end v_blank 12 h table 2 36 h end hsync 40 h table 2 37 h hsync detect window ff h 20 h recommend hsync detect window= 20 h 38 h -3f h reserved - 40 h -7f h test and unused - table 9. 8115 register summary (continued) sub- address control register reset/ default value use value comments table 10. product id register sub address = 00 h bit no. function description reset state 7-0 product id this 8-bit register specifies the last two digits of the product number. it is a read-only register. data written to it is ignored. 15 h table 11. input format register sub address = 01 h bit no. function description reset state 7 reserved 0 b 6-5 video timing standard these bits are read only unless d4 = 0. 00 = (m) ntsc 01 = (b, d, g, h, i, n) pal 10 = (m) pal 11 = combination (n) pal; also called (n c ) pal 00 b 4 auto detect video standard 0 = manual selection of video timing standard 1 = auto detect of video timing standard 1 b 3 setup select typically, this bit should be a 1 during (m) ntsc and (m, n) pal operation. otherwise, it should be a 0. 0 = video source has a 0 ire blanking pedestal 1 = video source has a 7.5 ire blanking pedestal 1 b 2-0 reserved 000 b HMP8115
24 table 12. output format register sub address = 02 h bit no. function description reset state 7-5 output color format 000 = 16-bit 4:2:2 ycbcr 001 = 8-bit 4:2:2 ycbcr 010 = 8-bit bt.656 011 = 15-bit rgb 100 = 16-bit rgb 101 = reserved 110 = reserved 111 = reserved 000 b 4-3 rgb gamma select these bits are ignored except during rgb output modes. 00 = linear rgb (gamma of input source = 2.2) 01 = linear rgb (gamma of input source = 2.8) 10 = gamma-corrected rgb (gamma = gamma of input source) 11 = reserved 00 b 2-1 output color select 00 = normal operation 01 = output blue field 10 = output black field 11 = output 75% color bars 00 b 0 vertical pixel siting this bit specifies whether or not the chrominance pixels have a half- line pixel offset from their associated luminance pixels. 0 = half-line offset 1 = aligned 0 b table 13. output control register sub address = 03 h bit no. function description reset state 7 video data output enable this bit is used to enable the p0-p15 outputs. 0 = outputs 3-stated 1 = outputs enabled 0 b 6 video timing output enable this bit is used to enable the hsync, vsync, blank, field, vbiv alid, d v alid, and intreq outputs. 0 = outputs 3-stated 1 = outputs enabled 0 b 5 field polarity 0 = active low (low during odd fields) 1 = active high (high during odd fields) 0 b 4 polarity blank 0 = active low (low during blanking) 1 = active high (high during blanking) 0 b 3 hsync polarity 0 = active low (low during horizontal sync) 1 = active high (high during horizontal sync) 0 b 2 vsync polarity 0 = active low (low during vertical sync) 1 = active high (high during vertical sync) 0 b 1 d v alid polarity 0 = active low (low during valid pixel data) 1 = active high (high during valid pixel data) 0 b 0 vbiv alid polarity 0 = active low (low during vbi data) 1 = active high (high during vbi data) 0 b HMP8115
25 table 14. genlock control register sub address = 04 h bit no. function description reset state 7 aspect ratio mode 0 = rectangular (bt.601) pixels 1 = square pixels 0 b 6 freeze output timing enable setting this bit to a 1 freezes the output timing at the end of the field. resetting this bit to a 0 resumes normal operation at the start of the next field. 0 = normal operation 1 = freeze output timing 0 b 5 d v alid duty cycle control (dvld_dcyc) this bit is ignored during the 8-bit ycbcr and bt.656 output modes. during 16-bit ycbcr, 15-bit rgb, or 16-bit rgb output modes, this bit is defined as: 0 = d v alid has 50/50 duty cycle at the pixel output datarate 1 = d v alid goes active based on linelock. this will cause d v alid to not have a 50/50 duty cycle. this bit is intended to be used in maintaining backward compatibilty with the hmp8112a d v alid output timing. 0 b 4 d v alid line tim- ing control (dvld_ltc) during 16-bit ycbcr, 15-bit rgb, or 16-bit rgb output modes, this bit is defined as: 0 = d v alid present only during active video time on active scan lines 1 = d v alid present the entire scan line time on all scan lines during the 8-bit ycbcr and bt.656 output modes, this bit defines the d v alid output sig- nal as: 0 = normal timing 1 = d v alid signal anded with clk2 0 b 3 missing hsync detect select this bit specifies the number of missing horizontal sync pulses before the device goes into the horizontal lock acquisition mode. in mode 0, the default value of the hpll ad- just register should be used. in mode 1, the typical values the hpll adjust register should be 10 h to 20 h . 0 = 12 pulses 1 = 1 pulse 0 b 2 missing vsync detect select this bit specifies the number of missing vertical sync pulses before the device goes into the vertical lock acquisition mode. 0 = 3 pulses 1 = 1 pulse 0 b 1-0 clk2 frequency this bit indicates the frequency of the clk2 input clock. 00 = 24.54mhz 01 = 27.0mhz 10 = 29.5mhz 11 = reserved 01 b table 15. analog input control register sub address = 05 h bit no. function description reset state 7-3 reserved 00000 b 2-0 video signal input select 000 = ntsc/pal 1 001 = ntsc/pal 2 010 = ntsc/pal 3 011 = s-video 100 = reserved 101 = reserved 110 = reserved 111 = reserved 000 b HMP8115
26 table 16. color processing register sub address = 06 h bit no. function description reset state 7-6 color gain control select if a value of 10, the color gain adjust register is used to specify the amount of color gain to be applied. 00 = no gain control (gain = 1x) 01 = automatic gain control 10 = fixed gain control 11 = freeze automatic gain control 01 b 5-4 color killer select 00 = force color on 01 = enable color killer 10 = reserved 11 = force color off 01 b 3-2 color coring select coring may be used to reduce low-level noise around zero (code 128) in the cbcr sig- nals. 00 = no coring 01 = 1 code coring 10 = 2 code coring 11 = 3 code coring 00 b 1 contrast control select this bit specifies whether the contrast control affects just the y data (0) or both the y and cbcr data (1). to avoid color shifts when changing contrast, this bit should be a 1. 0 = contrast controls only y data 1 = contrast controls y and cbcr data 1 b 0 color lowpass filter select this bit selects the bandwidth of the cbcr data. 0 = 850khz 1 = 1.5mhz 0 b table 17. luma processing register sub address = 08 h bit no. function description reset state 7-6 y filtering select the chroma trap filter may be used to remove any residual color subcarrier information from the y channel. during s-video operation, it should be disabled. during pal opera- tion, it should be enabled. the 3mhz lowpass filter may be used to remove high-frequen- cy noise. 00 = no filtering 01 = enable chroma trap filter 10 = enable 3.0mhz lowpass filter 11 = reserved 00 b 5-4 black level y coring select coring may be used to reduce low-level noise around black in the y signal. 00 = no coring 01 = 1 code coring 10 = 2 code coring 11 = 3 code coring 00 b 3-2 high frequency y coring select coring may be used to reduce high-frequency low-level noise in the y signal. 00 = no coring 01 = 1 code coring 10 = 2 code coring 11 = 3 code coring 01 b 1-0 sharpness frequency select if a value of 01 or 10, the sharpness adjust register is used to specify the amount of sharpness to be applied. 00 = bypass sharpness control 01 = maximum gain at 2.6mhz 10 = maximum gain at color subcarrier frequency 11 = reserved 00 b HMP8115
27 table 18. sliced vbi data enable register sub address = 0a h bit no. function description reset state 7-6 sliced closed captioning enable 00 = closed caption disabled 01 = closed caption enabled for odd fields: line 21 for ntsc, line 18 for (m) pal, or line 22 for (b, d, g, h, i, n, n c ) pal 10 = closed caption enabled for even fields: line 284 for ntsc, line 281 for (m) pal, or line 335 for (b, d, g, h, i, n, n c ) pal 11 = closed caption enabled for both odd and even fields 00 b 5-4 sliced wss enable 00 = wss disabled 01 = wss enabled for odd fields: line 20 for ntsc; line 17 for (m) pal, or line 23 for (b, d, g, h, i, n, n c ) pal 10 = wss enabled for even fields: line 283 for ntsc, line 280 for (m) pal, or line 336 for (b, d, g, h, i, n, n c ) pal 11 = wss enabled for both odd and even fields 00 b 3-2 sliced teletext enable 00 = teletext disabled 01 = teletext system b enabled 10 = teletext system c enabled 11 = reserved 00 b 1-0 reserved 00 b table 19. sliced vbi data output register sub address = 0b h bit no. function description reset state 7 sliced closed caption bt.656 output enable this bit specifies whether or not to output the caption data registers as bt.656 ancillary data. it is ignored unless captioning is enabled. access via the i 2 c interface is always available. 0 = do not output as bt.656 ancillary data 1 = output as bt.656 ancillary data 0 b 6 sliced wss bt.656 output enable this bit specifies whether or not to output the wss data registers as bt.656 ancillary data. it is ignored unless wss is enabled. access via the i 2 c interface is always available. 0 = do not output as bt.656 ancillary data 1 = output as bt.656 ancillary data 0 b 5 sliced teletext bt.656 output enable this bit specifies whether or not to output teletext data as bt.656 ancillary data. it is ig- nored unless teletext is enabled. 0 = do not output as bt.656 ancillary 1 = output as bt.656 ancillary data 0 b 4-1 reserved 0000 b 0 rtci bt.656 output enable this bit specifies whether or not to output rtci data as bt.656 ancillary data. 0 = do not output as bt.656 ancillary 1 = output as bt.656 ancillary data 0 b HMP8115
28 table 20. vbi data status register sub address = 0c h bit no. function description reset state 7 closed captioning odd field detect status this bit is read-only. data written to this bit is ignored. 0 = closed captioning not detected 1 = closed captioning detected 0 b 6 closed captioning even field detect status this bit is read-only. data written to this bit is ignored. 0 = closed captioning not detected 1 = closed captioning detected 0 b 5 wss odd field detect status this bit is read-only. data written to this bit is ignored. 0 = wss not detected 1 = wss detected 0 b 4 wss even field detect status this bit is read-only. data written to this bit is ignored. 0 = wss not detected 1 = wss detected 0 b 3 vbi teletext detect status this bit is read-only. data written to this bit is ignored. 0 = teletext not detected during vertical blanking interval 1 = teletext detected during vertical blanking interval 0 b 2-0 reserved 000 b table 21. video status register sub address = 0e h bit no. function description reset state 7 vertical lock status this bit is read-only. data written to this bit is ignored. 0 = not vertically locked 1 = vertically locked 0 b 6 horizontal lock status this bit is read-only. data written to this bit is ignored. 0 = not horizontally locked 1 = horizontally locked 0 b 5 color lock status this bit is read-only. data written to this bit is ignored. 0 = not color locked 1 = color locked 0 b 4 input video detect status this bit is read-only. data written to this bit is ignored. 0 = input video not detected on selected video input 1 = input video detected on selected video input 0 b 3-0 reserved 0000 b HMP8115
29 table 22. interrupt mask register sub address = 0f h bit no. function description reset state 7 genlock loss interrupt mask if this bit is a 1, an interrupt is generated when genlock is lost. 0 = interrupt disabled 1 = interrupt enabled 0 b 6 input signal loss interrupt mask if this bit is a 1, an interrupt is generated when a video signal is no longer detected on the selected video input. 0 = interrupt disabled 1 = interrupt enabled 0 b 5 closed caption interrupt mask if this bit is a 1, an interrupt is generated when the caption_odd_a and caption_odd_b or the caption_even_a and caption_even_b data registers contain new data. 0 = interrupt disabled 1 = interrupt enabled 0 b 4 wss interrupt mask if this bit is a 1, an interrupt is generated when the wss_odd_a and wss_odd_b or the wss_even_a and wss_even_b data registers contain new data. 0 = interrupt disabled 1 = interrupt enabled 0 b 3 teletext interrupt mask if this bit is a 1, an interrupt is generated when teletext information is first detected at the beginning of each field. 0 = interrupt disabled 1 = interrupt enabled 0 b 2-1 reserved 00 b 0 vertical sync interrupt mask if this bit is a 1, an interrupt is generated at the beginning of each field. 0 = interrupt disabled 1 = interrupt enabled 0 b table 23. interrupt status register sub address = 10 h bit no. function description reset state 7 genlock loss interrupt status if this bit is a 1, the reason for the interrupt request was that genlock was lost. to clear the interrupt request, a 1 must be written to this bit. 0 b 6 input signal loss interrupt status if this bit is a 1, the reason for the interrupt request was that the input video source is no longer present. to clear the interrupt request, a 1 must be written to this bit. 0 b 5 closed caption interrupt status if this bit is a 1, the reason for the interrupt request was that the caption_odd_a and caption_odd_b or the caption_even_a and caption_even_b data registers contain new data. to clear the interrupt request, a 1 must be written to this bit. 0 b 4 wss interrupt status if this bit is a 1, the reason for the interrupt request was that the wss_odd_a and wss_odd_b or the wss_even_a and wss_even_b data registers contain new da- ta. to clear the interrupt request, a 1 must be written to this bit. 0 b 3 teletext interrupt status if this bit is a 1, the reason for the interrupt request was that teletext data has been de- tected in the current field. to clear the interrupt request, a 1 must be written to this bit. 0 b 2-1 reserved 00 b 0 vertical sync interrupt status if this bit is a 1, the reason for the interrupt request was that a new field was started. to clear the interrupt request, a 1 must be written to this bit. 0 b HMP8115
30 table 24. brightness register sub address = 18 h bit no. function description reset state 7 reserved 0 b 6-0 brightness adjust these bits control the brightness. they may have a value of +63 (011 1111) to -64 (100 0000), with positive values increasing brightness. a value of 0 (000 0000) has no effect on the data. 0000000 b table 25. contrast register sub address = 19 h bit no. function description reset state 7-0 contrast adjust these bits control the contrast. they may have a value of 0x (0000 0000) to 1.992x (1111 1111). a value of 1x (1000 0000) has no effect on the data. 80 h table 26. hue register sub address = 1a h bit no. function description reset state 7-0 hue adjust these bits control the color hue. they may have a value of +30 degrees (0111 1111) to -30 degrees (1111 1111). a value of 0 degrees (0000 0000) has no effect on the color data. 00 h table 27. saturation register sub address = 1b h bit no. function description reset state 7-0 saturation adjust these bits control the color saturation. they may have a value of 0x (0000 0000) to 1.992x (1111 1111). a value of 1x (1000 0000) has no effect on the color data. a value of 0x (0000 0000) disables the color information. 80 h table 28. color gain register sub address = 1c h bit no. function description reset state 7-0 color gain adjust these bits control the amount of gain control for the color difference (cbcr) signals. they may have a value of 0.5x (0010 0000) to 3.98x (1111 1111). a value of 1x (0100 0000) has no effect on the data. this register is ignored unless the color gain control mode selection is fixed gain control. 40 h table 29. sharpness register sub address = 1e h bit no. function description reset state 7-6 reserved 00 b 5-0 sharpness adjust these bits control the amount of gain control of high frequency luminance signals (either 2.6mhz or fsc). they may have a value of +12db (11 1111) to -12db (00 0100). a value of 0db (01 0000) has no effect on the data. this register is ignored if the sharp- ness mode selection is disable sharpness control or reserved. 010000 b HMP8115
31 table 30. host control register sub address = 1f h bit no. function description reset state 7 software reset when this bit is set to 1, the entire device except the i 2 c bus is reset to a known state exactly like the reset input going active. the software reset will initialize all register bits to their reset state. once set this bit is self clearing after only 4 clk periods. this bit is cleared on power-up by the external reset pin. 0 b 6 reserved 0 b 5 closed caption odd field read status this bit is read-only. data written to this bit is ignored. the bit is cleared when the caption data has been read out via the i 2 c interface or as bt.656 ancillary data. 0 = no new caption data 1 = caption_odd_a and caption_odd_b data registers contain new data. 0 b 4 closed caption even field read status this bit is read-only. data written to this bit is ignored. the bit is cleared when the caption data has been read out via the i 2 c interface or as bt.656 ancillary data. 0 = no new caption data 1 = caption_even_a and caption_even_b data registers contain new data. 0 b 3 wss odd field read status this bit is read-only. data written to this bit is ignored. the bit is cleared when the wss data has been read out via the i 2 c interface or as bt.656 ancillary data. 0 = no new wss data 1 = wss_odd_a and wss_odd_b data registers contain new data. 0 b 2 wss even field read status this bit is read-only. data written to this bit is ignored. the bit is cleared when the wss data has been read out via the i 2 c interface or as bt.656 ancillary data. 0 = no new wss data 1 = wss_even_a and wss_even_b data registers contain new data. 0 b 1-0 reserved 00 b table 31. closed caption_odd_a data register sub address = 20 h bit no. function description reset state 7-0 odd field caption data if odd field captioning is enabled and present, this register is loaded with the first eight bits of caption data on line 18, 21, or 22. bit 0 corresponds to the first bit of caption infor- mation. data written to this register is ignored. 80 h table 32. closed caption_odd_b data register sub address = 21 h bit no. function description reset state 15-8 odd field caption data if odd field captioning is enabled and present, this register is loaded with the second eight bits of caption data on line 18, 21, or 22. data written to this register is ignored. 80 h table 33. closed caption_even_a data register sub address = 22 h bit no. function description reset state 7-0 even field caption data if even field captioning is enabled and present, this register is loaded with the first eight bits of caption data on line 281, 284, or 335. bit 0 corresponds to the first bit of caption information. data written to this register is ignored. 80 h HMP8115
32 table 34. closed caption_even_b data register sub address = 23 h bit no. function description reset state 15-8 even field caption data if even field captioning is enabled and present, this register is loaded with the second eight bits of caption data on line 281, 284, or 335. data written to this register is ignored. 80 h table 35. wss_odd_a data register sub address = 24 h bit no. function description reset state 7-0 odd field wss data if odd field wss is enabled and present, this register is loaded with the first eight bits of wss information on line 17, 20, or 23. bit 0 corresponds to the first bit of wss informa- tion. data written to this register is ignored. 00 h table 36. wss_odd_b data register sub address = 25 h bit no. function description reset state 15-14 reserved 00 b 13-8 odd field wss data if odd field wss is enabled and present, this register is loaded with the second six bits of wss information on line 17, 20, or 23. data written to this register is ignored. 000000 b table 37. wss_crc_odd data register sub address = 26 h bit no. function description reset state 7-6 reserved 00 b 5-0 odd field wss crc data if odd field wss is enabled and present during ntsc operation, this register is loaded with the six bits of crc information on line 20. it is always a 000000 during pal oper- ation. data written to this register is ignored. 000000 b table 38. wss_even_a data register sub address = 27 h bit no. function description reset state 7-0 even field wss data if even field wss is enabled and present, this register is loaded with the first eight bits of wss information on line 280, 283, or 336. bit 0 corresponds to the first bit of wss infor- mation. data written to this register is ignored. 00 h table 39. wss_even_b data register sub address = 28 h bit no. function description reset state 15-14 reserved 00 b 13-8 even field wss data if even field wss is enabled and present, this register is loaded with the second six bits of wss information on line 280, 283, or 336. data written to this register is ignored. 000000 b HMP8115
33 table 40. wss_crc_even data register sub address = 29 h bit no. function description reset state 7-6 reserved 00 b 5-0 even field wss crc data if even field wss is enabled and present during ntsc operation, this register is loaded with the six bits of crc information on line 283. it is always a 000000 during pal oper- ation. data written to this register is ignored. 000000 b table 41. start h_blank low register sub address = 30 h bit no. function description reset state 7-0 assert blank output signal this 8-bit register is cascaded with start h_blank high register to form a 10-bit start_horizontal_blank register. it specifies the horizontal count (in 1x clock cycles) at which to assert blank each scan line. bit 0 is always a 0, so the start of horizontal blanking may only be done with two pixel resolution. the leading edge of hsync is count 000 h . 4a h table 42. start h_blank high register sub address = 31 h bit no. function description reset state 15-10 reserved 000000 b 9-8 assert blank output signal this 2-bit register is cascaded with start h_blank low register to form a 10-bit start_horizontal_blank register. it specifies the horizontal count (in 1x clock cycles) at which to assert blank each scan line. the leading edge of hsync is count 000 h . 11 b table 43. end h_blank register sub address = 32 h bit no. function description reset state 7-0 negate blank output signal this 8-bit register specifies the horizontal count (in 1x clock cycles) at which to negate blankeach scan line. bit 0 is always a 0, so the end of horizontal blanking may only be done with two pixel resolution. the leading edge of hsync is count 000 h . 7a h table 44. start v_blank low register sub address = 33 h bit no. function description reset state 7-0 assert blank output signal this 8-bit register is cascaded with start v_blank high register to form a 9-bit start_vertical_blank register. it specifies the line number to assert blank each field. for ntsc operation, it occurs on line (n + 5) on odd fields and line (n + 268) on even fields. for pal operation, it occurs on line (n + 5) on odd fields and line (n + 318) on even fields. 02 h HMP8115
34 table 45. start v_blank high register sub address = 34 h bit no. function description reset state 15-9 reserved 0000000 b 8 assert blank output signal this 1-bit register is cascaded with start v_blank low register to form a 9-bit start_vertical_blank register. 1 b table 46. end v_blank register sub address = 35 h bit no. function description reset state 7-0 negate blank output signal this 8-bit register specifies the line number to negate blank each field. for ntsc operation, it occurs on line (n + 5) on odd fields and line (n + 268) on even fields. for pal operation, it occurs on line (n + 5) on odd fields and line (n + 318) on even fields. 12 h table 47. end hsync register sub address = 36 h bit no. function description reset state 7-0 negate hsync output signal this 8-bit register specifies the horizontal count at which to negate hsync each scan line. values may range from 0 (0000 0000) to 510 (1111 1111) clk2 cycles. the leading edge of hsync is count 00 h . 40 h table 48. hsync detect window register sub address = 37 h bit no. function description reset state 7-0 horizontal sync detect window this 8-bit register specifies the width of the window (in 1x clock samples) to look for hor- izontal sync pulses each line. the window is centered about where the horizontal sync pulse should be located. if the horizontal sync pulse falls inside this window, the digital pll will lock to it. if the hor- izontal sync pulse falls outside this window, the digital pll is immediately reset to have the same timing. recommend using a value of 20 h to optimize the response time of the digital pll. ff h HMP8115
35 pinout 80 lead pqfp top view 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 agnd vaa agnd ntsc/pal1 nc ntsc/pal3 ntsc/pal2 agnd agnd vaa agnd yout agnd vaa clk2 gnd v cc wpe gain_cntl ccap dec_l v cc gnd gnd reset nc gnd yin 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 p13 v cc p12 p11 p10 p9 p8 gnd v cc p7 p6 p5 p4 p3 gnd p2 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 gnd v cc dec_t lagc_cap lcap v cc nc gnd hsync vsync gnd v cc d v alid a/d_test nc c nc 63 62 61 p15 gnd vbiv alid 37 38 39 40 v cc clk2 gnd sda intreq p1 p0 scl 44 43 42 41 17 18 19 20 80 agnd nc field p14 agnd agnd agnd blank HMP8115
36 pin description pin name pin number input/ output description p0-p15 42, 43, 45, 47-51, 54-58, 60, 63, 64 o pixel output pins. see table 3. hsync 71 o horizontal sync output. hsync is asserted during the horizontal sync intervals. the polarity of hsync is programmable. this pin is three-stated after a reset or soft- ware reset and should be pulled high through a 10k resistor. vsync 70 o vertical sync output. vsync is asserted during the vertical sync intervals. the polar- ity of vsync is programmable. this pin is three-stated after a reset or software re- set and should be pulled high through a 10k resistor. field 67 o field output. the polarity of field is programmable. this pin is three-stated after a reset or software reset and should be pulled high through a 10k resistor. blank 65 o composite blanking output. blank is asserted during the horizontal and vertical blanking intervals. the polarity of is programmable. this pin is three-stated after a reset or software reset and should be pulled high through a 10k resistor. d v alid 66 o data valid output. d v alid is asserted during clk2 cycles that contain valid pixel da- ta. this pin is three-stated after a reset or software reset and should be pulled high through a 10k resistor. clk2 38, 13 i 2x pixel clock inputs. all clk2 pins must be connected together. this clock must be a continuous, free-running clock. reset 34 i reset control input. a logical zero for a minimum of four clk2 cycles resets the de- vice. reset must be a logical one for normal operation. sda 40 i/o i 2 c interface data input/output. scl 41 i i 2 c interface clock input. wpe 27 i white peak enable. when enabled (1), the video gain is reduced when the a/d out- put code exceeds 248. when disabled (0), the video ampli?er will clip when the a/d output code reaches code 255. vbiv alid 61 o vertical blanking interval valid output. vbiv alid is asserted during clk2 cycles that contain valid vbi (vertical blanking interval) data such as closed captioning, tele- text, and wide screen signalling data. the polarity of vbiv alid is programmable. this pin is three-stated after a reset or software reset and should be pulled high through a 10k resistor. intreq 44 o interrupt request output. this is an open-drain output and requires an external 10k pull-up resistor to v cc . ntsc/pal 1 7 i composite video input. this input must be ac-coupled to the video signal (using a 1 m f capacitor) and terminated with a 75 w resistor, as shown in the applications sec- tion. these components should be as close to this pin as possible for best perfor- mance. if not used, this pin should be connected to agnd through a 0.1 m f capacitor. ntsc/pal 2 6 i composite video input. this input must be ac-coupled to the video signal (using a 1 m f capacitor) and terminated with a 75 w resistor, as shown in the applications sec- tion. these components should be as close to this pin as possible for best perfor- mance. if not used, this pin should be connected to agnd through a 0.1 m f capacitor. ntsc/pal 3 (y) 5 i composite video or luminance (y) video input. this input must be ac-coupled to the video signal (using a 1 m f capacitor) and terminated with a 75 w resistor, as shown in the applications section. these components should be as close to this pin as possi- ble for best performance. if not used, this pin should be connected to agnd through a 0.1 m f capacitor. HMP8115
37 c 19 i chrominance (c) video input. this input must be ac-coupled to the video signal (us- inga1 m f capacitor) and terminated with a 75 w resistor, as shown in the applications section. these components, and the corresponding anti-aliasing lowpass ?lter, should be as close to this pin as possible for best performance. if not used, this pin should be connected to agnd through a 0.1 m f capacitor. yout 9 o analog output of the video multiplexer. this output should be lowpass ?ltered and in- put via the yin pin, as shown in the applications section. the anti-aliasing lowpass ?lter should be as close to yout and yin as possible for best performance. yin 8 i analog input to the adc. gain_ctrl 28 i gain control input. a dc voltage is used to set the video ampli?ers gain, as shown in figure 2. the reference circuit should be as close to this pin as possible for best performance. dec_t 78 i decoupling for a/d converter reference. a 0.1 m f capacitor should be connected be- tween this pin and agnd, as shown in the applications section. this capacitor should be as close to this pin as possible for best performance. dec_l 30 i decoupling for a/d converter reference. a 0.1 m f capacitor should be connected be- tween this pin and agnd, as shown in the applications section. this capacitor should be as close to this pin as possible for best performance. lagc_cap 77 i capacitor connection for luminance agc circuit. controls the agc loop time con- stant. a 0.01 m f capacitor should be connected between this pin and agnd, as shown in the applications section. this capacitor should be as close to this pin as possible for best performance. lcap 76 i capacitor connection for luminance clamp circuit. controls the clamp loop time con- stant. a 0.047 m f capacitor should be connected between this pin and agnd, as shown in the applications section. this capacitor should be as close to this pin as possible for best performance. ccap 29 i capacitor connection for chrominance clamp circuit. controls the clamp loop time constant. a 0.047 m f capacitor should be connected between this pin and agnd, as shown in the applications section. this capacitor should be as close to this pin as possible for best performance. v cc 26, 31,37, 52, 59, 68, 75, 79 i digital power supply pins. all v cc pins must be connected together. gnd 25, 33, 35, 36, 39, 46, 53, 62, 69, 72, 80 i digital ground pins. all gnd pins must be connected together. vaa 2, 12,14 i analog power supply pins. all vaa pins must be connected together. agnd 1, 3, 10, 11, 15,16, 21, 22, 23, 24 i analog ground pins. all agnd pins must be connected together. a/d test 17 o a/d test pin. this pin must be left ?oating for proper operation. nc 4, 18, 20, 32, 73, 74 no connect pins. these pins must be left ?oating for proper operation. pin description (continued) pin name pin number input/ output description HMP8115
38 applications information pcb layout considerations a pcb board with a minimum of 4 layers is recommended, with layers 1 and 4 (top and bottom) for signals and layers 2 and 3 for power and ground. the pcb layout should imple- ment the lowest possible noise on the power and ground planes by providing excellent decoupling. the optimum layout places the HMP8115 as close as possi- ble to the power supply connector and the video input con- nector. component placement external components should be positioned as close as pos- sible to the appropriate pin, ideally such that traces can be connected point to point. chip capacitors are recommended where possible, with radial lead ceramic capacitors the sec- ond-best choice. power supply decoupling should be done using a 0.1 m f ceramic capacitor in parallel with a 0.01 m f chip capacitor for each group of v aa and v cc pins to ground. these capaci- tors should be located as close to the power and ground pins as possible, using short, wide traces. digital ground plane all gnd pins on the HMP8115 should be connected to the digital ground plane of the board. analog ground plane a separate analog ground plane for the HMP8115 is recom- mended. all agnd pins on the HMP8115 should be con- nected to the analog ground plane. this analog ground plane should be connected to the boards digital ground plane at a single point. analog power plane the HMP8115 should have its own v aa power plane that is isolated from the common power plane of the board, with a gap between the two power planes of at least 1/8 inch. all v aa pins on the HMP8115 must be connected to this analog power plane. the analog power plane should be connected to the boards normal v cc power plane at a single point though a low-resistance ferrite bead, such as a ferroxcube 5659065-3b, fair-rite 2743001111, or tdk bf45-4001. the ferrite bead provides resistance to switching currents, improving the performance of HMP8115. a single 47 m f capacitor should also be used between the analog power plane and the ground plane to control low-frequency power supply ripple. if a separate linear regulator is used to provide power to the analog power plane, the power-up sequence should be designed to ensure latchup will not occur. a separate linear reg- ulator is recommended if the power supply noise on the v aa pins exceeds 200mv. analog signals traces containing digital signals should not be routed over, under, or adjacent to the analog output traces to minimize crosstalk. if this is not possible, coupling can be minimized by routing the digital signals at a 90 degree angle to the ana- log signals. the analog input traces should also not overlay the v aa power plane to maximize high-frequency power sup- ply rejection. evaluation board hmpvideval/isa the hmpvideval/isa evaluation board allows connecting the HMP8115 into a pc isa slot for evaluation. it includes the HMP8115 ntsc/pal decoder, 3mb of vram, and a ntsc/pal encoder. the board accepts composite or s-video input and displays video on a standard tv. the isa bus and evaluation software allow easy performance evalua- tion of the HMP8115 using tools such as the tektronix vm700 video test system. related application notes application notes are also available on the intersil multime- dia web site at http://www.semi.harris.com/mmedia. an9644 : composite video separation techniques an9716 : widescreen signalling (wss) an9717 : ycbcr to rgb considerations an9728 : bt.656 video interface for ics an9738 : video module interface (vmi) for ics HMP8115
39 r 4 75 jp 1 jumper v aa r 8 50 c 12 15pf r 7 10k 27mhz 64 63 60 58 57 56 55 54 p15 p14 p13 p12 p11 p10 p9 p8 65 66 67 71 70 blank d v alid field hsync vsync wpe reset sda scl clk2 clk2 test yout yin lagc_cap lcap ccap gain_cntl dec_t dec_l ntsc/pal 1 ntsc/pal 2 ntsc/pal 3 c u1 p7 p6 p5 p4 p3 p2 p1 p0 51 50 49 48 47 45 43 42 p[15..8] p[7..0] r 16 4k r 17 4k v cc reset 27mhz scl 27 34 40 41 38 13 36 7 6 5 19 9 8 78 sda blank d v alid field hsync c 1 1.0 m f ntsc-pal1 chroma v aa 77 76 29 28 30 c 10 0.1 m f c 11 0.01 m f c 8 0.1 m f c 9 0.01 m f r 5 1k r 6 750 c 7 0.047 m f c 6 0.047 m f c 5 0.01 m f r 3 75 ntsc-pal2 ntsc-pal3/y r 2 75 r 1 75 c 2 1.0 m f c 3 1.0 m f anti-alias c 4 1.0 m f filter anti-alias filter 61 vbiv alid figure 22. HMP8115 reference schematics vsync vbiv alid 44 intreq intreq v cc rp1 10k v cc HMP8115
40 absolute maximum ratings thermal information digital supply voltage (v cc to gnd) . . . . . . . . . . . . . . . . . . . . 7.0v analog supply voltage (vaa to gnd) . . . . . . . . . . . . . . . . . . . . 7.0v digital input voltages . . . . . . . . . . . . . . . gnd - 0.5v to v cc + 0.5v esd classi?cation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . class 1 operating temperature range HMP8115cn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 o c to 70 o c thermal resistance (typical, see note 42) q ja ( o c/w) pqfp package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 maximum power dissipation HMP8115cn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.9w maximum storage temperature range . . . . . . . . . .-65 o c to 150 o c maximum junction temperatures . . . . . . . . . . . . . . . . . . . . . 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . 300 o c caution: stresses above those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operatio n of the device at these or any other conditions above those indicated in the operational sections of this speci?cation is not im plied. note: 42. q ja is measured with the component mounted on an evaluation pc board in free air. dissipation rating assumes device is mounted with all leads soldered to printed circuit board. electrical speci?cations v cc = v aa = 5.0v, t a = 25 o c parameter symbol test condition min typ max units power supply characteristics power supply voltage range v cc , v aa (note 43) 4.75 5 5.25 v total power supply current i tot clk2 = 29.5mhz, v cc = vaa = 5.25v outputs not loaded - 280 315 ma digital power supply current i cc - 105 115 ma analog power supply current i aa - 175 200 ma total power dissipation p tot clk2 = 29.5mhz, v cc = vaa = 5.25v, outputs not loaded - 1.47 1.66 w dc characteristics: digital i/o (except clk2 and i 2 c interface) input logic high voltage v ih v cc = max 2.0 - - v input logic low voltage v il v cc = min - - 0.8 v output logic high voltage v oh i oh = -4ma, v cc = max 2.4 - - v output logic low voltage v ol i ol = 4ma, v cc = min - - 0.4 v input leakage current i ih , i il v cc = max input = 0v or 5v - - 10 m a input/output capacitance c in , c out f = 1mhz, (note 43) all measurements referenced to ground, t a = 25 o c -8-pf three-state output current leakage i oz --10 m a dc characteristics: clk2 digital input input logic high voltage v ih v cc = max 0.7xv cc --v input logic low voltage v il v cc = min - - 0.3xv cc v input leakage current i ih v cc = max input = 0v or v cc --10 m a i il - 450 - - m a input capacitance c in clk2 = 1mhz, (note 43) all measurements referenced to ground, t a = 25 o c -8-pf HMP8115
41 dc characteristics: i 2 c interface input logic high voltage v ih v cc = max 0.7xv cc --v input logic low voltage v il v cc = min - - 0.3xv cc v output logic high voltage v oh i oh = -1ma, v cc = max 3.0 - - v output logic low voltage v ol i ol = 3ma, v cc = min 0 - 0.4 v input leakage current i ih , i il v cc = max input = 0v or 5v --10 m a input/output capacitance c in , c out scl = 400khz, (note 43) all measurements referenced to gnd, t a = 25 o c -8-pf ac characteristics: digital i/o (except i 2 c interface) clk2 frequency 20 - 29.5 mhz clk2 waveform symmetry (note 43) 40 - 60 % clk2 pulse width high t pwh 13 - - ns clk2 pulse width low t pwl 13 - - ns data and control setup time t su (note 44) 10 - - ns data and control hold time t hd 0- -ns clk2 to output delay t dvld 058ns data and control rise/fall time t r , t f (note 43) - 2 6 ns ac characteristics: i 2 c interface scl clock frequency f scl 0 - 400 khz scl pulse width low t low 1.3 - - m s scl pulse width high t high 0.6 - - m s data hold time t hd:data 0- -ns data setup time t su:data 100 - - ns sda, scl rise time t r (note43) - - 300 ns sda, scl fall time t f - - 300 ns analog input performance composite video input amplitude (sync tip to white level) input termination of 75 w and 1.0 m f ac-coupled 0.5 1.0 2.0 v p-p luminance (y) video input amplitude (sync tip to white level) input termination of 75 w and 1.0 m f ac-coupled 0.5 1.0 2.0 v p-p chrominance (c) video input amplitude (burst amplitude) input termination of 75 w and 1.0 m f ac-coupled, (note 43) 0.143 0.286 0.6 v p-p video input impedance r ain note 43 200 - - k w electrical speci?cations v cc = v aa = 5.0v, t a = 25 o c (continued) parameter symbol test condition min typ max units HMP8115
42 video input bandwidth bw 1v p-p sine wave input to -3dbc reduction, (note 43) 5 - - mhz adc input range a in full scale - 1 - v p-p a in offset - 1.5 - v adc integral nonlinearity inl best fit linearity - 2 - lsb adc differential nonlinearity dnl - 0.35 - lsb video performance differential gain dg modulated ramp (note 43) - 2 - % differential phase dp - 1 - deg. hue accuracy 75% color bars (note 43) - 2 - deg. color saturation accuracy - 2 - % luminance nonlinearity ntc-7 composite (note 43) - 2 - % snr snrl weighted pedestal input (note 43) - 50 - db genlock performance horizontal locking time t lock time from initial lock acquisition to an error of 1 pixel. (note 43) 2 3 - fields long-term horizontal sync lock range range over specified pixel jitter is maintained. assumes line time changes by amount indicat- ed slowly between over one field. (note 43) -- 5 % number of missing horizontal syncs before lost lock declared h sync lost programmable via register 04 h (note 43) 1 or 12 1 or 12 1 or 12 hsyncs number of missing vertical syncs before lost lock declared v sync lost 1 or 3 1 or 3 1 or 3 vsyncs long-term color subcarrier lock range range over color subcarrier locking time and accuracy spec- ifications are maintained. sub- carrier frequency changes by amount indicated slowly over 24 hours. (note 43) - 200 400 hz vertical sample alignment (notes 43, 45) - 1/8 - pixel -10-ns notes: 43. guaranteed by design or characterization. 44. test performed with c l = 40pf, i ol = 4ma, i oh = -4ma. input reference level is 1.5v for all inputs. v ih = 3.0v, v il = 0v. 45. this should not be confused with clock jitter, since the HMP8115 does not generate the sample clock. thus, clock jitter is solely depen- dent on the source of the clk2 signal. the vertical sample alignment parameter specifies how accurately samples align vertically from one scan line to the next. electrical speci?cations v cc = v aa = 5.0v, t a = 25 o c (continued) parameter symbol test condition min typ max units HMP8115
43 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?cation. intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/or specifications at a ny time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to b e accurate and reli- able. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third p arties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its sub sidiaries. for information regarding intersil corporation and its products, see web site http://www.intersil.com sales of?ce headquarters north america intersil corporation p. o. box 883, mail stop 53-204 melbourne, fl 32902 tel: (407) 724-7000 fax: (407) 724-7240 europe intersil sa mercure center 100, rue de la fusee 1130 brussels, belgium tel: (32) 2.724.2111 fax: (32) 2.724.22.05 asia intersil (taiwan) ltd. taiwan limited 7f-6, no. 101 fu hsing north road taipei, taiwan republic of china tel: (886) 2 2716 9310 fax: (886) 2 2715 3029 HMP8115 metric plastic quad flatpack packages (mqfp/pqfp) d d1 e e1 -a- pin 1 a2 a1 a 5 o -16 o 5 o -16 o 0 o -7 o 0.40 0.016 min l 0 o min plane b 0.005/0.009 0.13/0.23 with plating base metal seating 0.005/0.007 0.13/0.17 b1 -b- e 0.008 0.20 a-b s d s c m 0.10 0.004 -c- -d- -h- q80.14x20 (jedec mo-108cb-1 issue a) 80 lead metric plastic quad flatpack package sym- bol inches millimeters notes min max min max a - 0.134 - 3.40 - a1 0.010 - 0.25 - - a2 0.100 0.120 2.55 3.05 - b 0.012 0.018 0.30 0.45 6 b1 0.012 0.016 0.30 0.40 - d 0.904 0.923 22.95 23.45 3 d1 0.783 0.791 19.90 20.10 4, 5 e 0.667 0.687 16.95 17.45 3 e1 0.547 0.555 13.90 14.10 4, 5 l 0.026 0.037 0.65 0.95 - n80 807 e 0.032 bsc 0.80 bsc - nd 24 24 - ne 16 16 - rev. 0 1/94 notes: 1. controlling dimension: millimeter. converted inch dimensions are not necessarily exact. 2. all dimensions and tolerances per ansi y14.5m-1982. 3. dimensions d and e to be determined at seating plane . 4. dimensions d1 and e1 to be determined at datum plane . 5. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25mm (0.010 inch) per side. 6. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.08mm (0.003 inch) total. 7. n is the number of terminal positions. -c- -h-


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